In advanced technology nodes, wiring structures are becoming ever smaller with minimum ground rules reaching feature sizes of 10 nm and less. In integrated circuits, the wiring structures on different wiring layers can be interconnected by fully aligned vias. The fully aligned vias provide the benefit of landing directly on the wiring structures having the minimum ground rule, as well as larger sized features.
In current fabrication processes, the fully aligned vias are formed in a same manner for accessing both the wiring structures having the minimum ground rule and the larger sized features. This results in a reduced volume of conductor material within the larger sized features, increasing its overall resistance.